Integrated circuit devices such as transistors are formed over semiconductor wafers. The devices are interconnected through metal lines and vias to form functional circuits, wherein the metal lines and vias are formed in back-end-of-line processes. To reduce the parasitic capacitance of the metal lines and vias, the metal lines and vias are formed in low-k dielectric layers, which typically have k values lower than 3.8, lower than 3.0, or lower than 2.5.
In the formation of the metal lines and vias, the low-k dielectric material is etched to form trenches and via openings. The etching of the low-k dielectric material may involve forming a metal hard mask and a silicon carbide layer over the low-k dielectric material, and using the patterned metal hard mask as an etching mask to form trenches. Via openings are also formed and self aligned to the trenches. The trenches and the via openings are then filled with a metallic material, which may comprise copper. A chemical mechanical polish (CMP) is then performed to remove excess portions of the metallic material over the low-k dielectric material.
It has been found that when the widths of the low-k dielectric lines become very small, for example, when the respective circuits are formed using 28 nm technology or 20 nm technology, line bending may occur to low-k dielectric lines that are in neighboring trenches. Since the metallic material is filled into the trenches and via openings, the bending of the low-k dielectric lines causes the distortion of the resulting metal lines, and sometimes the breaking of the metal lines and vias.